soc: x86: add Lakemont SoC #32104
Merged
soc: x86: add Lakemont SoC #32104
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
This also includes #31198. Will rebase once that is merged. |
github-actions
bot
added
area: API
dcpleung
force-pushed
the
soc_x86_lakemont
branch
2 times, most recently
from
a604e06 to
4695cb7
Compare
dcpleung
requested review from
aasthagr,
jenmwms,
jhedberg and
nashif
as code owners
|
#31198 is merged. So this is ready for review. |
jhedberg
approved these changes
Feb 16, 2021
jenmwms
reviewed
Feb 16, 2021
jenmwms
approved these changes
Feb 16, 2021
aasthagr
approved these changes
Feb 16, 2021
|
CI failure is related to #32344 |
|
can we have a user of this? maybe in qemu? |
This is an hidden option to indicate we are building for PC-compatible devices (where there are BIOS, ACPI, etc. which are standard on such devices). Signed-off-by: Daniel Leung <[email protected]>
This adds a new kconfig to enable the use of memory map. This map can be populated automatically if CONFIG_MULTIBOOT_MEMMAP=y or can be manually defined via x86_memmap[]. Signed-off-by: Daniel Leung <[email protected]>
Tells QEMU to enable CPU flags corresponding to MMX/SSE kconfigs. Signed-off-by: Daniel Leung <[email protected]>
This adds a very basic SoC configuration for Intel Lakemont SoC. Signed-off-by: Daniel Leung <[email protected]>
dcpleung
force-pushed
the
soc_x86_lakemont
branch
from
4695cb7 to
f6b0042
Compare
github-actions
bot
added
area: Boards
area: Devicetree
area: Devicetree Binding
Added a new QEMU board in last push. |
dcpleung
force-pushed
the
soc_x86_lakemont
branch
2 times, most recently
from
9274a76 to
fee5435
Compare
nashif
reviewed
Feb 19, 2021
This adds a new board qemu_x86_lakemont for testing the Lakemont SoC configuration. Signed-off-by: Daniel Leung <[email protected]>
This adds qemu_x86_lakemont to the platform allow list for the FPU sharing tests. Since Lakemont supports SSE3 and SSSE3, it is better to test them also. Signed-off-by: Daniel Leung <[email protected]>
dcpleung
force-pushed
the
soc_x86_lakemont
branch
from
fee5435 to
0cd1f8c
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This adds a very basic SoC configuration for Intel Lakemont SoC.